View MMM6035_466811.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Freescale Semiconductor Advance Information
Document Number: MMM6035/D Rev. 2.4, 10/2005
MMM6035
MMM6035
Quad-Band GSM/GPRS PA Module with Integrated Power Control
Device MMM6035
Package Information Plastic Package Case 1561 (6 x 6 mm Module) Ordering Information Device Marking or Operating Temperature Range MMM6035 Package Module
1
Introduction
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 Functional Block Diagram . . . . . . . . . . . . . . . 2 3 Electrical Characteristics . . . . . . . . . . . . . . . 3 4 RF Specifications . . . . . . . . . . . . . . . . . . . . . . 4 5 Input/Output ESD Specifications . . . . . . . . . 9 6 Application Information . . . . . . . . . . . . . . . . 11 7 Design Information . . . . . . . . . . . . . . . . . . . . 14 8 Package Information . . . . . . . . . . . . . . . . . . 18 9 Signal Description . . . . . . . . . . . . . . . . . . . . 20 10Product Documentation . . . . . . . . . . . . . . . 21
The MMM6035 is a 50 Power Amplifier module for quad-, tri-, and dual-band GSM handset applications, functioning over the GSM850, EGSM, DCS, and PCS frequency bands. This module is compatible with GSM/GPRS operating modes (up to 50% duty cycle). To simplify radio front-end design requirements, the power control function is integrated, removing the need for directional couplers and detector diodes. GSM burst shaping and power control is integrated on an internal control SmartMOSTM IC. The analog power control signal is smoothed by a low-pass filter included in the internal control SmartMOS chip, allowing over 45 dB dynamic range to be achieved. The MMM6035 also prevents degradation of switching transients, regardless of battery conditions, due to an internal anti-saturation detection feature. Transmit Enable and Band Select functions are controlled through 0 to 2.8 V logic inputs. These functions are also compatible with 0 to 1.8 V logic inputs.
This document contains information on a new product. Specifications and information herein are subject to change without notice. (c) Freescale Semiconductor, Inc., 2005. All rights reserved.
Functional Block Diagram
2
Functional Block Diagram
Figure 1 is a functional block diagram of the quad-band (GSM850, EGSM, DCS, and PCS power amplifier module.
VDD3_HB_DEC
VDD1_HB
VDD2_HB
VRAMP
LB_HB
TX_EN
VREG
Power Control IC
MATCH MATCH
VBAT
VD_OUT
TXIN_HB
MATCH
PRE DRIVER
DRIVER
FINAL
MATCH
TXOUT_HB
VREG_PA
VAPC
VREG_PA
LB_HB_B
TXIN_LB
MATCH
PRE DRIVER
DRIVER
FINAL
MATCH
TXOUT_LB
MATCH
MATCH
VDD1_LB
Figure 1. Functional Block Diagram
MMM6035 Advance Information, Rev. 2.4 2 Freescale Semiconductor
VDD2_LB
Electrical Characteristics
3
Electrical Characteristics
Table 1. Maximum Ratings
Rating Symbol VDD VBAT VREG Pin TA Tstg TJ MSL Rth Value 5.5 5.5 5.5 11 -20 to 85 -55 to 150 150 3 20 C/W Unit V V V dBm C C C
Drain Supply Voltages Power Control IC Supply Voltage External Regulated DC Supply Voltage RF Input Power Operating Temperature Range Storage Temperature Junction Temperature Moisture Sensitivity Level (Meets lead-free reflow profiles with peak temperature of 260 C) Thermal Resistance (junction to mounting base)
NOTES: 1. Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits in the Recommended Operating Conditions and Electrical Characteristics tables.
Table 2. Recommended Operating Conditions
Characteristic External Regulated DC Supply Voltage Power Control IC Supply Voltage RF Input Power Mode Control Low Voltage (TX_EN, LB_HB) Mode Control High Voltage (TX_EN, LB_HB) Power Control Ramp Voltage VRAMP Symbol VREG VBAT Pin Min 2.6 3.1 3.0 0 1.4 0.1 Typ 2.8 Max 3.0 4.5 9.0 0.4 VREG 2.2 Unit V V dBm V V V
Table 3. DC Characteristics (VREG = 2.6 to 3 V, TA = -20 to 85 C)
Characteristic External Regulate DC Supply Current TX_EN, LB_HB high Standby Leakage Current Include current on all pins TX_EN, LB_HB low VRAMP = 0 V, Vreg = 2.8 V, VBAT = 4.5 V, TA = 85 C Mode Control Input Input Low Input High Symbol Ireg Min Typ 5 Max 10 Unit mA
ILKG
-
-
50
A
A Imci(L) Imci(H) -0.5 50
MMM6035 Advance Information, Rev. 2.4 Freescale Semiconductor 3
RF Specifications
Table 3. DC Characteristics (continued) (VREG = 2.6 to 3 V, TA = -20 to 85 C)
Characteristic Mode Control Input Resistance (High State) Resistance to GND Vramp Input Current VRAMP = 0 V Vramp = 2.2 V Symbol Rmci Min Typ 250 Max Unit k A IRAMP(L) IRAMP(H) -0.5 50
4
RF Specifications
Table 4. Mode GMSK Cellular Band Specifications
(TXIN_LB = 3.0 dBm, VBAT = 3.6 V, VRAMP = 0.1 to 2.2 V pulsed, Period = 4.6 ms, Duty Cycle = 25%, LB_HB = 0 V, VREG = 2.8 V, TX_EN = 2.8 V, TA = 25C 5 C, unless otherwise noted) Characteristic Symbol F0 PO(H) PO(HX) PAE IDD(L) Iso1 2 F0 3 F0 NRx1 FRX = 869-894 MHz IN Xtalk VSWR Min 824 34.2 32.2 46 6:1 Typ 34.9 52 16 Max 849 150 -20 -10 -10 -82 -15 Unit MHz dBm dBm % mA dBm dBm dBm dB dBm
Operating Frequency Output Power at High VRAMP Output Power over VRNG, TRNG at High VRAMP Power Added Efficiency @ PO(H) Current Consumption at Low Output Power (PO set to 6.0 dBm) Forward Isolation (VRAMP = 0 V, TX_EN = 0 V) over VRNG, TRNG Harmonics level over VRNG, TRNG Tx Noise in Rx Cellular Band @ PO=PO(H) RBW = 100 kHz Input VSWR Second Harmonic Leakage at DCS/PCS over VRNG, TRNG at High VRAMP Load mismatch stability All angles Set Vramp where Po(H) 34.2 dBm into 50 load All spurious < -36 dBm, RBW = 3 MHz Load mismatch ruggedness All angles Set Vramp where Po(H) 34.2 dBm into 50 load No damage, no degradation Power Control Range over VRNG, TRNG
VSWR
20:1
-
-
RPC
35
-
-
dB
MMM6035 Advance Information, Rev. 2.4 4 Freescale Semiconductor
RF Specifications
Table 5. Mode GMSK E-GSM Band Specifications
(TXIN_LB = 3.0 dBm, VBAT = 3.6 V, VRAMP = 0.1 to 2.2 V pulsed, Period = 4.6 ms, Duty Cycle = 25%, LB_HB = 0 V, VREG = 2.8 V, TX_EN = 2.8 V, TA = 25 C 5 C unless otherwise noted) Characteristic Operating Frequency Output Power at High VRAMP Output Power over VRNG, TRNG at High VRAMP Power Added Efficiency @ PO(H) Current Consumption at Low Output Power (PO set to 6.0 dBm) Forward Isolation (VRAMP = 0 V, TX_EN = 0 V) over VRNG, TRNG Harmonics level over VRNG, TRNG Tx Noise in Rx E-GSM Band @ PO = PO(H) RBW = 100 kHz NRx1 FRX = 925-935 MHz NRx2 FRX = 935-960 MHz Input VSWR Second Harmonic Leakage at DCS/PCS over VRNG, TRNG at High VRAMP Load mismatch stability All angles Set Vramp where Po(H) 34.2 dBm into 50 load All spurious < -36 dBm, RBW = 3 MHz Load mismatch ruggedness All angles Set Vramp where Po(H) 34.2 dBm into 50 load No damage, no degradation Power Control Range over VRNG, TRNG IN Xtalk VSWR Symbol F0 PO(H) PO(Hx) PAE IDD(L) Iso1 2 F0 3 F0 Min 880 34.2 32.2 50 Typ 34.9 56 Max 915 150 -20 -10 -10 Unit MHz dBm dBm % mA dBm dBm dBm 6:1 12 -77 -82 -15 dB dBm
VSWR
20:1
-
-
RPC
35
-
-
dB
Table 6. Mode GMSK DCS Band Specifications
(TXIN_HB = 3 dBm, VBAT = 3.6 V, VRAMP = 0.1 to 2.2 V pulsed, Period = 4.6 ms, Duty Cycle = 25%, LB_HB = 2.8 V, VREG = 2.8 V, TX_EN = 2.8 V, TA = 25 C 5 C unless otherwise noted) Characteristic Operating Frequency Output Power at High VRAMP Output Power over VRNG, TRNG at High VRAMP Power Added Efficiency @ PO(H) Current Consumption at Low Output Power (PO set to 1.5 dBm) Forward Isolation (VRAMP = 0 V, TX_EN = 0 V) over VRNG, TRNG Symbol F0 PO(H) PO(Hx) PAE IDD(L) Iso1 Min 1710 31.5 29.5 40 Typ 33.0 46 Max 1785 150 -28 Unit MHz dBm dBm % mA dBm
MMM6035 Advance Information, Rev. 2.4 Freescale Semiconductor 5
RF Specifications
Table 6. Mode GMSK DCS Band Specifications (continued)
(TXIN_HB = 3 dBm, VBAT = 3.6 V, VRAMP = 0.1 to 2.2 V pulsed, Period = 4.6 ms, Duty Cycle = 25%, LB_HB = 2.8 V, VREG = 2.8 V, TX_EN = 2.8 V, TA = 25 C 5 C unless otherwise noted) Characteristic Harmonics level over VRNG, TRNG Tx Noise in Rx DCS Band @ PO = PO(H) RBW = 100 kHz Input VSWR Load mismatch stability All angles Set Vramp where Po(H) 31.5 dBm into 50 load All spurious < -30 dBm, RBW = 3 MHz Load mismatch ruggedness All angles Set Vramp where Po(H) 34.2 dBm into 50 load No damage, no degradation Power Control Range over VRNG, TRNG Symbol 2F0 3F0 NRx1 FRX = 1805-1880 MHz IN VSWR Min Typ Max -10 -10 -75 Unit dBm dBm
6:1
16 -
-
dB
VSWR
20:1
-
-
RPC
35
-
-
dB
Table 7. Mode GMSK PCS Band Specifications
(TXIN_HB = 3 dBm, VBAT = 3.6 V, VRAMP = 0.1 to 2.2 V pulsed, Period = 4.6 ms, Duty Cycle = 25%, LB_HB = 2.8 V, VREG = 2.8 V, TX_EN = 2.8 V, TA = 25 C 5 C unless otherwise noted) Characteristic Operating Frequency Output Power at High VRAMP Output Power over VRNG, TRNG at High VRAMP Power Added Efficiency @ PO(H) Current Consumption at Low Output Power (PO set to 1.5 dBm) Forward Isolation (VRAMP = 0 V, TX_EN = 0 V) over VRNG, TRNG Harmonics level over VRNG, TRNG Tx Noise in Rx PCS Band @ PO = PO(H) RBW = 100 kHz Input VSWR Load mismatch stability All angles Set Vramp where Po(H) 31.5 dBm into 50 load All spurious < -30 dBm, RBW = 3 MHz Symbol F0 PO(H) PO(Hx) PAE IDD(L) Iso1 2F0 3F0 NRx1 FRX = 1930 -1990 MHz IN VSWR Min 1850 31.5 29.5 40 Typ 32.8 46 Max 1910 150 -28 -10 -10 -75 Unit MHz dBm dBm % mA dBm dBm dBm
6:1
15 -
-
dB
MMM6035 Advance Information, Rev. 2.4 6 Freescale Semiconductor
RF Specifications
Table 7. Mode GMSK PCS Band Specifications (continued)
(TXIN_HB = 3 dBm, VBAT = 3.6 V, VRAMP = 0.1 to 2.2 V pulsed, Period = 4.6 ms, Duty Cycle = 25%, LB_HB = 2.8 V, VREG = 2.8 V, TX_EN = 2.8 V, TA = 25 C 5 C unless otherwise noted) Characteristic Load mismatch ruggedness All angles Set Vramp where Po(H) 34.2 dBm into 50 load No damage, no degradation Power Control Range over VRNG, TRNG Symbol VSWR Min 20:1 Typ Max Unit
RPC
35
-
-
dB
Table 8. Power Control Specifications
(VREG = 2.8 V, Vrng = 3.0 to 4.5 V, -20 to 85 C) Characteristic Wake-up Time Conditions VBAT = 3.6 V TA = 25 C, Time to reach stable VD_OUT after 0.3 V VRAMP step Voltage at which VD_OUT rises above 0V VBAT = 3.6 V TA = 25 C, VRAMP > VOffset VBAT = 3.6 V TA = 25 C, Po>5 dBm for TX CEL and EGSM, Po>0 dBm for TX DCS and PCS VBAT = 3.6 V TA = 25 C, Rising VRAMP VBAT = 3.6 V TA = 25 C, Falling VRAMP VBAT = 3.6 V TA = 25 C VBAT = 3.6 V VBAT = 3.6 V TA = 25 C Symbol twu Min Typ 12 Max Unit s
Vramp Input Voltage Offset
Voffset1
0.18
0.2
-
V
VD_OUT vs. VRAMP Slope
Vslope1
-
2.0
-
V/V
Po versus VRAMP Slope
Po_slope1
-
-
240
dB/V
VRAMP Controller Enable Threshold
Vctrl(R)
-
160
-
mV
VRAMP Controller Disable Threshold
Vctrl(F)
-
140
-
mV
Smoothing Filter Bandwidth (3 dB cutoff frequency) Smoothing Filter Attenuation (Atten at 1 MHz) Smoothing Filter Rise Time (Vdout rise time between 10% and 90% with VRAMP step of Voffset 50 mV)
BW vramp
-
200 30 2.5
-
kHz dB s
vramp
tr
MMM6035 Advance Information, Rev. 2.4 Freescale Semiconductor 7
RF Specifications
Table 8. Power Control Specifications (continued)
(VREG = 2.8 V, Vrng = 3.0 to 4.5 V, -20 to 85 C) Characteristic Pout variation versus Temp Vramp adj for Pout(H)-10 dB < Pout < Pout(H) Vramp adj for Pout(H)-20 dB < Pout < Pout(H)-10 dB Vramp adj for Pout(H)-30 dB < Pout < Pout(H)-20 dB Pout variation versus Freq Vramp set for Power(H) at 836.5 MHz Vramp set for Power(H) at 897.5 MHz Vramp set for Power(H) at 1747.5 MHz Vramp set for Power(H) at 1880 MHz
1
Conditions VBAT = 3.6 V TA = 25 C
Symbol Po(H)_T Po(M)_T Po(L)_T
Min
Typ
Max
Unit
-1.5 -2.0 -4.0
-
1.5 2.0 4.0
dB dB dB
VBAT = 3.6 V TA = 25 C
Po_CELL_f Po_EGSM_f Po_DCS_f Po_PCS_f
-0.5 -0.5 -0.5
-
0.5 0.5 0.5
dB dB dB
-0.5
-
0.5
dB
See Figure 4.
MMM6035 Advance Information, Rev. 2.4 8 Freescale Semiconductor
Input/Output ESD Specifications
5
Input/Output ESD Specifications
The MMM6035 meets Class 1B and Class 1C for the Human Body Model (HBM) Electrostatic Discharge (ESD) classification and it meets Class M2 for the Machine Model (MM) ESD classification. Table 9 and Table 10 show the ESD immunity level for each MMM6035 pin. The numbers shown in Table 9 and Table 10 specify the ESD threshold level for each pin where the I-V curve between the pin and ground begins to show degradation.
Table 9. ESD Human Body Model: EOS/ESD-S5.1 (Pin to Ground Stress)
Pin Number-Name 1 - GND 2 - VDD2_HB 3 - VDD1_HB 4 - Vapc 5 - TXIn_HB 6 - TXIn_LB 7 - VDD1_LB 8 - VDD2_LB 9 - GND 10 - GND 11 - TXOut_LB 12 - Vreg_PA 13 - VD_OUT 14 - Vramp 15 - TXEn 16 - LB_HB 17 - Vreg 18 - Vbat 19 - VD3_HB_DEC 20 - TXOut_HB 21 - GND 22 - GND NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA X X NA NA NA NA X X X X X X X X X X NA NA X X X X 450 Volts NA 500 Volts NA 750 Volts NA 1000 Volts NA 1250 Volts NA 2000 Volts NA X
MMM6035 Advance Information, Rev. 2.4 Freescale Semiconductor 9
Input/Output ESD Specifications
Table 10. ESD Machine Model: EOS/ESD-S5.1, From 50 V up to 150 V (Destruction Voltage)
Pin Number/Name 1 - GND 2 - VDD2_HB 3 - VDD1_HB 4 - Vapc 5 - TXIn_HB 6 - TXIn_LB 7 - VDD1_LB 8 - VDD2_LB 9 - GND 10 - GND 11 - TXOut_LB 12 - Vreg_PA 13 - VD_OUT 14 - Vramp 15 - TXEn 16 - LB_HB 17 - Vreg 18 - Vbat 19 - VD3_HB_DEC 20 - TXOut_HB 21 - GND 22 - GND NA NA NA NA NA NA NA NA NA NA NA NA X X NA NA X X X X X X X X X X NA NA NA NA NA NA 50 Volts NA 75 Volts NA X X X X X 100 Volts NA 150 Volts NA 200 Volts NA
MMM6035 Advance Information, Rev. 2.4 10 Freescale Semiconductor
Application Information
6
Application Information
Figure 2 shows the typical application schematic and Figure 3 shows the printed circuit board for the MMM6035. The bill of materials are listed in Table 11 and the power up/down sequences are listed in Table 12.
Figure 2. Typical Application Schematic
MMM6035 Advance Information, Rev. 2.4 Freescale Semiconductor 11
Application Information
Table 11. Bill of Materials
Reference C1 C2 C3 C4 C5 C6 C7 C9 C10 C11 C12 C13 C14 C15 L1 R1 R2 R3 R4 Value 68 uF 6 V 1000 nF 100 nF 22 pF 22 pF 2.7 pF 22 pF 33 pF 8.2 pF 10 nF 10 nF 220 pF 10 nF 1 nF 3.9 nH 10 k 10k 1.8 k 1k Size and Manufacturer Sprague 0402 Murata 0402 Murata 0402 Murata 0402 Murata 0402 Murata 0402 Murata 0402 Murata 0201 Johanson 0402 Murata 0402 Murata 0402 Murata 0402 Murata 0402 Murata 0402 Murata 0402 NEOHM 0402 NEOHM 0402 NEOHM 0402 NEOHM
MMM6035 Advance Information, Rev. 2.4 12 Freescale Semiconductor
Application Information
60 mm
50 mm
Figure 3. Printed Circuit Board Table 12. Power Up/Down Sequences
SEQ Power Up Sequence for TX 1 2 3 4 5 6 7 8 Set TX_EN, LB_HB low Set VRAMP to 0 V Apply VBAT Apply RF drive to appropriate TXIN Apply VREG Set LB_HB for desired band Set TX_EN high Apply appropriate pulses to VRAMP DESCRIPTION
Power Down Sequence for TX 1 2 3 4 Set VRAMP to 0 V Set TX_EN low Set LB_HB low Remove VREG
MMM6035 Advance Information, Rev. 2.4 Freescale Semiconductor 13
Design Information
Table 12. Power Up/Down Sequences (continued)
SEQ 5 6 Remove RF drive Remove VBAT DESCRIPTION
7
7.1
Design Information
Power Control
Open loop power control of the power amplifier is enabled when TX_EN is set high. The PA drain voltage will then be proportional to the VRAMP input voltage over the range 200 mV to 2.2 V of VRAMP as shown in Figure 4.
VBAT disabled enabled Vsat Vslope
VD_OUT
section
Controller
0 Vctrl
Voffset Vramp
Figure 4. VD_OUT vs. VRAMP Characteristics
14
Controller
section
MMM6035 Advance Information, Rev. 2.4 Freescale Semiconductor
Design Information
To meet the GSM power versus time mask and switching transient requirement, the MMM6035 must be provided with a DAC ramp profile on the VRAMP input, as well as proper timing on digital controls for the control loop circuitry as shown in Figure 5.
twu tr_ramp TX_EN tf_ramp
Vramp(H)
Vramp Vpedestal Voffset Vramp(L)
VD_OUT
+4dBc -6dBc* Pout (dB) -30dBc* Iso2 Iso1 10s 8s 10s 542.8s 10s 8s 10s
* Derated at low Pout
Figure 5. Recommended Power Control Timing
The ramp profile consists of a pedestal voltage, 12 to 16 discrete voltage steps on the rising edge of the burst, a constant region, 12 to 16 steps on the falling edge of the burst, and a final voltage. Generally, the same profile, scaled in amplitude, us used for all frequencies and power control levels. A feature unique to the MMM6035 is the internal offset generator which functions to cancel any external offset associated with the DAC driving the VRAMP pin. In addition, the MMM6035 has a 200 kHz
MMM6035 Advance Information, Rev. 2.4 Freescale Semiconductor 15
Design Information
two-pole Sallenkey filter included in the VRAMP path to remove DAC noise and to provide VRAMP signal smoothing.
7.2
Anti-Saturation Detection Feature
The MMM6035 prevents degradation of switching transients, regardless of battery conditions, due to an internal anti-saturation detection feature. The goal of this block is to maintain the RF output power ramp within the power versus time mask and to maintain acceptable spectral limits at specified offset frequencies. The anti-saturation detection feature is implemented by a feedback loop inside the power control loop which detects when the power controller PMOS goes into the linear region. The feedback loop reduces VRAMP to maintain the pass device in its saturation region, even under low battery voltage conditions.
40 35 30 25 20 Pout (dBm) 15 10 5 0 -5 -10 -15 0 2 4 6 8 10 Time (us) 12 14 16 18 20 VBATT = 3.0V Antisat on VBATT = 3.5V Antisat on Time Mask
VBATT = 3.0V Ant isat off
Figure 6. Anti-Saturation Detection
7.3
Recommended Power Control Calibration Procedure
Power control calibration is carried out at two points. The procedure first requires the measurement of output power (Po) calibration points at two values of Vramp (Vramp(1) and Vramp(2)). Figure 5 shows these points, after conversion (*), plotted on the RMS RF output voltage (Vrf) against the control voltage (Vramp) characteristic. Using these points, the Vramp voltage (Vramp(E)) can be estimated for any desired output power level. In order to meet the transmitted power level versus time requirement of GSM05.05 Specification, at the lowest power level, it is also necessary to determine the Vramp pedestal voltage (see Figure 4 and Figure 5) required to reach an acceptable power level when the controller section feedback loop has stabilized after wake-up. As a reminder:
Vrf = 10
( Po - 13 ) 20
Eqn. 1
where Po is in dBm into 50 and Vrf is in Vrms.
MMM6035 Advance Information, Rev. 2.4 16 Freescale Semiconductor
Design Information
Vrf Vrms Calibration point(2) Vrf(2) Estimated point Vrf(E)
Vrf(1) Vrf(P) 0
Calibration point(1)
Vpedestal Vramp(1)
Vramp(E)
Vramp(2)
Vramp (V)
Figure 7. Vrf vs. Vramp characteristic
The calibration points Vrf(1) and Vrf(2) are each measured by forcing Vramp levels of Vramp(1) and Vramp(2) respectively. The estimated Vramp level for the required RF output voltage Vrf(E) is then calculated from the following:
Vramp ( 2 )x [ Vrf ( E ) - Vrf ( 1 ) ] + Vramp ( 1 )x [ Vrf ( 2 ) - Vrf ( E ) ] Vramp ( E ) = --------------------------------------------------------------------------------------------------------------------------------------------------------------Vrf ( 2 ) - Vrf ( 1 )
Eqn. 1
In a similar way Vpedestal can be calculated:
Vramp ( 2 )x [ Vrf ( P ) - Vrf ( 1 ) ] + Vramp ( 1 )x [ Vrf ( 2 ) - Vrf ( P ) ] Vpedestal = ------------------------------------------------------------------------------------------------------------------------------------------------------------Vrf ( 2 ) - Vrf ( 1 )
Eqn. 2
Table 13. Recommended Calibration Values
Description Vramp at calibration point (1) Vramp at calibration point (2) Output power with Vramp=Vpedestal (Low band) Output power with Vramp=Vpedestal (High band) Active Vramp rise time Active Vramp fall time Pedestal Width Symbol Vramp(1) Vramp(2) Po(P)_LB Po(P)_HB Tr_ramp Tf_ramp Value 0.3 1.5 1 -3.5 14 14 12 Unit V V dBm dBm s s s
MMM6035 Advance Information, Rev. 2.4 Freescale Semiconductor 17
Package Information
8
Package Information
VDD3_HB_DEC TXOUT_HB TX_EN 15 LB_HB 16 VREG 17 VBAT 18 19 GND 1 20
GND
14
VRAMP
13
VD_OUT
VDD2_ HB
2 12 VREG_PA
VDD1_HB
3 GND 11 TXOUT_LB
VAPC
4
TXIN_HB
5 6 TXIN_LB 7 VDD1_LB 8 VDD2_LB 9 GND
10
GND
Figure 8. Package Footprint - Top View
MMM6035 Advance Information, Rev. 2.4 18 Freescale Semiconductor
Package Information
Figure 9. Outline Dimensions for 6x6 mm Module (Case 1561-01, Issue O)
MMM6035 Advance Information, Rev. 2.4 Freescale Semiconductor 19
Signal Description
9
Signal Description
Table 14. Pin Connections
Name GND VDD2_HB VDD1_HB VAPC TX_IN_HB TX_IN_LB VDD1_LB VDD2_LB GND GND TXOUT_LB VREG_PA Ground Drain Supply for Driver Stage, High-Band Drain Supply for Pre-Driver Stage, High-Band Bias Control Voltage TX Input High-Band TX Input Low-Band Drain Supply for Pre-Driver Stage, Low-Band Drain Supply for Driver Stage, Low-Band Ground Ground TX Output Low-Band Regulated DC supply output active only when TX_EN is high. Used for external biasing of the power amplifier section. Power Control IC Output DAC power control ramp Enable Power Control when set High Low-Band/High-Band Select. Logic High for High-Band, Logic Low for Low-Band. External Regulated Voltage Drain supply for power control chip Supply RF Input RF Input Supply Supply Ground Ground Ground Ground 50 - NOT DC Blocked 50 - DC Blocked 50 - DC Blocked Description Type Ground Supply Supply Impedance Ground
Number 1 2 3 4 5 6 7 8 9 10 11 12
13 14 15 16 17 18 19 20
VD_OUT VRAMP TX_EN LB_HB VREG VBAT
Supply Control Control Control Supply Supply RF RF Output 50 - NOT DC Blocked
VDD3_HB_DEC High-Band Final Stage RF Decoupling TXOUT_HB TX Output High-Band
MMM6035 Advance Information, Rev. 2.4 20 Freescale Semiconductor
Product Documentation
10 Product Documentation
This data sheet provides an abbreviated version of the full data sheet for the stated device. The full data sheet is labeled as a particular type: Product Preview, Advance Information, or Technical Data. Definitions of these types are available at: http://www.freescale.com on the Documentation page.
MMM6035 Advance Information, Rev. 2.4 Freescale Semiconductor 21
How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) support@freescale.com Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064, Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T., Hong Kong +800 2666 8080 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-521-6274 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com
Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. (c) Freescale Semiconductor, Inc. 2005. All rights reserved.
RoHS-compliant and/or Pb- free versions of Freescale products have the functionality and electrical characteristics of their non-RoHS-compliant and/or non-Pb- free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. For information on Freescale.s Environmental Products program, go to http://www.freescale.com/epp.
Document Number: MMM6035/D Rev. 2.4 10/2005

▲Up To Search▲

Price & Availability of MMM6035

	To Download MMM6035 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .